1. Field of the Invention
The present invention relates generally to reducing coupling between adjacent signal lines and signal bumps and compensation for impedance, capacitance and inductance through matching conductive line lengths for a flip-chip type semiconductor device. Particularly, the invention includes ground bumps extending from at least one ground plane that are adjacent the signal bumps to reduce coupling between adjacent signal bumps and signal lines having matched lengths to simplify compensation circuitry.
2. State of the Art
Interconnection and packaging-related issues are among the factors that determine not only the number of circuits that can be integrated on a chip but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced sizes of transistors and enlarged chip dimensions. The industry has come to realize that merely having a fast chip will not necessarily result in a fast system; the fast chip must also be supported by equally fast and reliable connections. Essentially, the connections, in conjunction with the packaging, supply the chip with signals and power and redistribute the tightly packed terminals of the chip to the terminals of a carrier substrate such as a printed wiring board.
FIGS. 1 and 2 illustrate a prior art flip-chip semiconductor device 2 in conjunction with a carrier substrate 4. Flip-chip technology, including its fabrication and use, is well known to those of ordinary skill in the art as this technology has been in use and developed for over 30 years. As shown in FIG. 1, a flip-chip semiconductor device 2 conventionally comprises an active semiconductor die 6 having an active surface 8 and active surface contacts or bond pads 10. A dielectric layer 12, for example, of silicon dioxide or silicon nitride, is formed over the active surface 8 by techniques well known in the art. Vias 14 are defined in dielectric layer 12, for example, using well-known photolithographic techniques to mask and pattern the dielectric layer 12 and etch same, for example, with buffered HF to expose the contacts or bond pads 10 of the active surface 8. The bond pads 10 may be connected to traces of an electrical interconnect layer 16 on the dielectric layer 12 in the form of power, ground and signal lines 17 in a well-known manner, for example, by evaporating or sputtering aluminum or an alloy thereof, followed by masking and etching. The power, ground and signal lines 17 of the electrical interconnect layer 16 enable the relatively compact array of bond pads 10 to be distributed over a broader surface area. Solder bumps 18, or balls, are placed upon ends of the signal lines 17 of the electrical interconnect layer 16 to enable electrical coupling with contact pads 20 on the carrier substrate 4, such as a printed wiring board. The flip-chip semiconductor device 2, with the solder bumps 18, is inverted so that its front surface 24 faces toward the top surface 26 of the carrier substrate 4, with each solder bump 18 on the flip-chip semiconductor device 2 being positioned on the appropriate contact pad 20 of the carrier substrate 4. The assembly of the flip-chip semiconductor device 2 and the carrier substrate 4 is then heated so as to liquify the solder bumps 18 and thus connect each bond pad 10 on the flip-chip semiconductor device 2 to an associated contact pad 20 on the carrier substrate 4.
Because the flip-chip type arrangement does not require leads coupled to the active surface of a semiconductor die and extending beyond the lateral periphery thereof, it provides a compact assembly in terms of the die""s xe2x80x9cfootprint.xe2x80x9d In other words, the area of the carrier substrate 4 occupied by the contact pads 20 is, for a given size semiconductor die, the same or less than that occupied by the die itself. Furthermore, the contacts on the semiconductor die, in the form of solder bumps 18, may be arranged in a so-called xe2x80x9carea arrayxe2x80x9d disposed over substantially the entire active surface or front face of the die. Flip-chip type mounting techniques, therefore, are well suited for use with semiconductor dice having large numbers of bond pads, in contrast to wire bonding type and tape-automated type mounting techniques which are far more limiting in terms of the number of bond pads which may reasonably and reliably be employed. As a result of the use of flip-chip type mounting techniques, the maximum number of I/O and power/ground terminals available for the semiconductor die can be increased, and signal and power/ground interconnections can be more efficiently routed on the die. Examples of methods of fabricating semiconductor die assemblies using flip-chip type and other type techniques are described in U.S. Pat. No. 6,048,753 to Farnworth et al. (Apr. 11, 2000), U.S. Pat. No. 6,018,196 to Noddin (Jan. 25, 2000), U.S. Pat. No. 6,020,220 to Gilleo et al. (Feb. 1, 2000), U.S. Pat. No. 5,950,304 to Khandros et al. (Sep. 14, 1999), and U.S. Pat. No. 4,833,521 to Early (May 23, 1989).
As with any conductive line carrying a signal, signal lines for integrated circuits generate electromagnetic and electrostatic fields. These electromagnetic and electrostatic fields may affect the signals carried in adjacent signal lines unless some form of compensation is used. It is known to use a ground plane to couple the cross-talk from a signal line in a semiconductor assembly.
An example of a semiconductor assembly having a ground plane is illustrated and described in U.S. Pat. No. 6,020,637 to Karnezos (Feb. 1, 2000), the disclosure of which is hereby incorporated herein by reference. The Karnezos reference discloses an interconnect substrate having an aperture therein which is attached to a heat spreader. A ground plane is provided on the interconnect substrate and a chip is back bonded to the heat spreader in the aperture of the interconnect substrate. Signal bumps and ground bumps are formed on the interconnect substrate, the signal bumps interconnecting with traces and bond wires to the chip and the ground bumps interconnecting with the ground plane. However, in some instances, the interconnect substrate in the Karnezos reference is large and not conducive to limiting the xe2x80x9creal estatexe2x80x9d required for a particular chip due to the wire bond assembly thereof. While in additional instances, the adjacent signal bumps and signal lines are likely to produce electromagnetic and electrostatic coupling therebetween. Furthermore, none of the ground planes are formed directly on the chip.
Electromagnetic and electrostatic coupling between signal lines, or xe2x80x9ccross-talk,xe2x80x9d is undesirable because it increases the load of the signal lines and may create noise and signal delays. The primary factors affecting cross-talk include the surface area of the signal line directed to an adjacent signal line, which includes signal line length, the distance between the signal lines and the dielectric constant (xcex5r) of the material between the signal lines. For flip-chip type semiconductor devices, where a large number of contacts with attached signal lines are used to carry signals to various locations for convenient access, impedance changes and cross-talk can be a significant factor affecting the speed and signal integrity of the device and system in which it is connected.
One further aspect of flip-chip type semiconductor device packaging which adds to the complexity of matching the loads and delays and, therefore, the signal integrity of the lines is the varying external line lengths between bond pads or other contacts on a semiconductor die and the connections of the substrate on which the die is mounted. To achieve a faster system and therefore shortest delay in a semiconductor device environment, conventional wisdom encourages the shortest signal line possible because the shorter the distance the signal needs to travel, the faster it arrives. As a result, when a signal line path is designed for placement on a semiconductor die, or other carrier substrate, it is typically designed with each signal line having an optimal path such that it travels on as short a path as possible, given the overall layout of all the signal line paths. In other words, the signal lines travel in as direct a path as possible from their origins to their destinations, with some variance to accommodate for the paths of other signal lines and positions of various components. For a given semiconductor die architecture matched to a given I/O array architecture for a specific application, existing signal line lengths are, therefore, varied. Because the load of the signal line is, in part, dependent upon the length of the signal line, the loads of the signal lines of varied length will, therefore, also be varied. Furthermore, due to varied signal line lengths, signals traveling on those signal lines of different lengths have varied travel times and associated delays.
When the loads and delays on multiple signal lines fed by a common die are equal, the signal strength of the overall system is strongest and signal transfer is most reliable. Mismatches of characteristic impedance between the signal lines may cause undesirable signal reflections and delays. It is most desirable to have equal impedance loads or a constant characteristic impedance on each signal line associated with a semiconductor die, as viewed from the die. To accomplish this, a method used with flip-chip type and other type packaging is to add inductors and capacitors to balance the load on each signal line as seen by the semiconductor die. Adding inductors and capacitors, however, while helpful in balancing mismatched loads, is a difficult way to match loads precisely to a given system in all environments, is relatively more expensive than without such capacitors and inductors, and undesirably increases the power consumed and heat produced by the system.
Therefore, it is desirable to have a flip-chip type packaged semiconductor device having matched characteristic loads on its respective signal lines, as viewed by the semiconductor die, without the heat-producing and power-consuming capacitors and inductors used previously. Further, it is also desirable to have a flip-chip type semiconductor device that prevents or reduces electromagnetic and electrostatic coupling between adjacent signal lines and interconnections.
The present invention provides a relatively inexpensive alternative to the inductors and capacitors conventionally used to match impedance for flip-chip type signal lines for semiconductor devices. According to the present invention, each signal line on a flip-chip type semiconductor device has substantially a common length, regardless of the signal line""s origin and destination on the device. By adding bends and direction changes into the conventional paths of signal lines on a flip-chip type device, the overall length of each of the signal lines may be made substantially equal. Additionally, a ground plane may be placed above or below a signal line layer, or both above and below it, separated from the signal line layer by a dielectric layer. By placing a ground plane near the signal line layer, the signal lines are isolated from the active surface of the semiconductor die or the signal lines on a circuit board, or both, and a reference is created for matching impedance. Further, a ball grid array on the flip-chip type device may be configured to have both ground bumps and signal bumps arranged in a manner to further isolate electromagnetic and electrostatic coupling between adjacent signal bumps. The ground plane further allows signals on the various signal lines to have a return path to the source. By the signal lines each having a common electrical length, they also have a common capacitance, inductance and impedance, common time required for signal propagation, and other common characteristics and thus do not require compensation using inductors and capacitors.
A method of manufacturing flip-chip type semiconductor devices is disclosed wherein a first dielectric passivation layer is deposited on a surface of a semiconductor die having bond pads, and portions of the first passivation layer are removed to expose the bond pads. A conductive layer is deposited over the first dielectric passivation layer, and portions of the conductive layer are removed to define ground, power or signal lines, or traces, extending in substantially common lengths to locations for conductive elements. A second dielectric passivation layer is deposited over the conductive signal lines, and portions of the second passivation layer are removed to allow access to the conductive signal lines at the conductive element locations. A ground plane is deposited over portions of the second passivation layer, leaving the conductive element locations exposed and surrounded by a border of dielectric material. A dielectric layer is deposited over portions of the ground plane to insulate the ground plane from the conductive elements which are coupled to the conductive signal lines at the conductive element locations. Alternatively or additionally, a ground plane may be deposited before the conductive signal line layer and separated from it by an additional dielectric passivation layer and borders of dielectric material through which conductive elements may extend from the semiconductor die surface to the conductive element locations. In an alternative embodiment, ground conductive elements are coupled to the ground plane and are positioned substantially adjacently planar with the conductive elements coupled to the signal lines.
An electronic system is disclosed comprising a processor, a memory device, an input, an output and a storage device, at least one of which includes a flip-chip type semiconductor device having signal lines, each of a substantially common length. A semiconductor wafer is disclosed having at least one flip-chip type semiconductor device having signal lines, each of a substantially common length.